The Instruction Set

The 6502 has a relatively basic set of instructions, many having similar functions (e.g. memory access, arithmetic, etc.). The following sections list the complete set of 56 instructions in functional groups.

Load/Store Operations

These instructions transfer a single byte between memory and one of the registers. Load operations set the negative (N) and zero (Z) flags depending on the value of transferred. Store operations do not affect the flag settings.

LDALoad AccumulatorN,Z
LDXLoad X RegisterN,Z
LDYLoad Y RegisterN,Z
STAStore Accumulator 
STXStore X Register 
STYStore Y Register 

Register Transfers

The contents of the X and Y registers can be moved to or from the accumulator, setting the negative (N) and zero (Z) flags as appropriate.

TAXTransfer accumulator to XN,Z
TAYTransfer accumulator to YN,Z
TXATransfer X to accumulatorN,Z
TYATransfer Y to accumulatorN,Z

Stack Operations

The 6502 microprocessor supports a 256 byte stack fixed between memory locations $0100 and $01FF. A special 8-bit register, S, is used to keep track of the next free byte of stack space. Pushing a byte on to the stack causes the value to be stored at the current free location (e.g. $0100,S) and then the stack pointer is post decremented. Pull operations reverse this procedure.

The stack register can only be accessed by transferring its value to or from the X register. Its value is automatically modified by push/pull instructions, subroutine calls and returns, interrupts and returns from interrupts.

TSXTransfer stack pointer to XN,Z
TXSTransfer X to stack pointer 
PHAPush accumulator on stack 
PHPPush processor status on stack 
PLAPull accumulator from stackN,Z
PLPPull processor status from stackAll


The following instructions perform logical operations on the contents of the accumulator and another value held in memory. The BIT instruction performs a logical AND to test the presence of bits in the memory value to set the flags but does not keep the result.

EORExclusive ORN,Z
ORALogical Inclusive ORN,Z
BITBit TestN,V,Z


The arithmetic operations perform addition and subtraction on the contents of the accumulator. The compare operations allow the comparison of the accumulator and X or Y with memory values.

ADCAdd with CarryN,V,Z,C
SBCSubtract with CarryN,V,Z,C
CMPCompare accumulatorN,Z,C
CPXCompare X registerN,Z,C
CPYCompare Y registerN,Z,C

Increments & Decrements

Increment or decrement a memory location or one of the X or Y registers by one setting the negative (N) and zero (Z) flags as appropriate,

INCIncrement a memory locationN,Z
INXIncrement the X registerN,Z
INYIncrement the Y registerN,Z
DECDecrement a memory locationN,Z
DEXDecrement the X registerN,Z
DEYDecrement the Y registerN,Z


Shift instructions cause the bits within either a memory location or the accumulator to be shifted by one bit position. The rotate instructions use the contents if the carry flag (C) to fill the vacant position generated by the shift and to catch the overflowing bit. The arithmetic and logical shifts shift in an appropriate 0 or 1 bit as appropriate but catch the overflow bit in the carry flag (C).

ASLArithmetic Shift LeftN,Z,C
LSRLogical Shift RightN,Z,C
ROLRotate LeftN,Z,C
RORRotate RightN,Z,C

Jumps & Calls

The following instructions modify the program counter causing a break to normal sequential execution. The JSR instruction pushes the old PC onto the stack before changing it to the new location allowing a subsequent RTS to return execution to the instruction after the call.

JMPJump to another location 
JSRJump to a subroutine 
RTSReturn from subroutine 


Branch instructions break the normal sequential flow of execution by changing the program counter if a specified condition is met. All the conditions are based on examining a single bit within the processor status.

BCCBranch if carry flag clear 
BCSBranch if carry flag set 
BEQBranch if zero flag set 
BMIBranch if negative flag set 
BNEBranch if zero flag clear 
BPLBranch if negative flag clear 
BVCBranch if overflow flag clear 
BVSBranch if overflow flag set 

Branch instructions use relative address to identify the target instruction if they are executed. As relative addresses are stored using a signed 8 bit byte the target instruction must be within 126 bytes before the branch or 128 bytes after the branch.

Status Flag Changes

The following instructions change the values of specific status flags.

CLCClear carry flagC
CLDClear decimal mode flagD
CLIClear interrupt disable flagI
CLVClear overflow flagV
SECSet carry flagC
SEDSet decimal mode flagD
SEISet interrupt disable flagI

System Functions

The remaining instructions perform useful but rarely used functions.

BRKForce an interruptB
NOPNo Operation 
RTIReturn from InterruptAll
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This page was last updated on 2nd January 2002